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CXA2112R
LCD Driver For the availability of this product, please contact the sales office.
Description The CXA2112R is a driver IC developed for use in the 6-input/12-input Sony polysilicon TFT LCD panel (LCX016/017). It has a line invert amplifier and analog de-multiplexers, timing generator and output buffers required for these. CXA2112R can directly drive analog inputs of LCX016/017. It is used one IC with the LCX016, and two ICs with the LCX017. The VCOM setting circuit and pre-charge pulse waveform generator are also on-chip. 64 pin LQFP (Plastic)
Features * High-speed signal processing supports XGA high refresh signal (dot clock to 100MHz) * Overall wide band response * Low output deviation by on-chip output offset cancel circuit * Small phase delay difference between inverted signal and non-inverted signal * On-chip timing generator with ECL * Dot clock phase adjustment function * VCOM voltage generation circuit * Pre-charge pulse waveform generation circuit Absolute Maximum Ratings * Supply voltage * Supply voltage * Operating temperature * Storage temperature * Allowable power dissipation Operating Conditions * Supply voltage * Supply voltage
VCC VDD
PD
16 5.5 -20 to +70 -65 to +150 2300
V V C C mW (single layered board mounted)
VCC VDD
15 to 15.5 4.75 to 5.25
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E97801A81-PS
CXA2112R
Block Diagram
VCOMOFST
34
SID_IN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
33
DLY_CNT 49 MCLK 50 MCLK/ 51 INV_CNT 52 S/H VDD 53 CLK_OUT 54 CLK_OUT/ 55 OFFSET CANCEL D.P 56 D.P 57 DGND 58 CLK_IN 59 NC 60 CLK_IN/ 61 PRG 62 NC 63 NC 64 offset cancel mode timing S/H TIMING GENERATOR S/H Pulses S/H S/H S/H S/H BUFFER D CLOCK DELAY S/H S/H S/H BUFFER INVERT AMP SID BIAS VCOM
VCOMOUT
VIDEO_IN
SID_OFST
INV_OUT
OFFSET
SID_OUT
D.P
D.P
SIGCEN
SH_IN
VCC
ISET
FRP
NC
32 GND2 31 SH_OUT1 30 NC 29 SH_OUT2 28 NC OFFSET CANCEL 27 SH_OUT3 S/H S/H BUFFER 26 PVCC 25 D.P 24 D.P BUFFER 23 PGND 22 NC BUFFER 21 SH_OUT4 20 NC BUFFER 19 SH_OUT5 18 NC 17 SH_OUT6
OFFSET CANCEL S/H S/H
OFFSET CANCEL S/H S/H S/H
OFFSET CANCEL S/H S/H
OFFSET CANCEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
ENB
DIR_CNT
NC
POS_CNT1
D.P
NC
POS_CNT2
D.P
NC
NEXT_OUT
S/12_CNT
NEXT_IN
F/R_CNT
-2-
NC
NC
CXA2112R
Pin Description Pin No. Symbol I/O Standard voltage level Equivalent circuit Description
1
POS_CNT1 I See Table A-1.
1 2
VDD VDD 60k 2k 20 1.6V
Sample-and-hold position setting. See Tables A-1, A-2 and A-3.
2
POS_CNT2
20 10
VDD
VDD
3
NEXT_OUT
O
Approx. 4V
3
Connect as closely as possible to NEXT_IN.
600
VDD VDD 0.7k
4
NEXT_IN
I
4
Connect as closely as possible to NEXT_OUT.
16k
5
F/R_CNT
I
High: 2.5V Low: 0.8V OPEN High
VDD VDD VDD VDD VDD 10k 100k
Before/after decision for 12-output. See Table B.
10k 100k 20k
10
S/12_CNT
I
High: 2.5V Low: 0.8V OPEN High
5 10
25 100k
6-output/12-output switch. High: 6-output Low: 12-output. See Table B.
VDD VDD VDD 50k 150k
12
ENB
I
High: 2.5V Low: 0.8V
145 12 50k
Horizontal sync signal ENB input. Refer to Timing Chart.
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CXA2112R
Pin No.
Symbol
I/O
Standard voltage level
Equivalent circuit
Description
VDD VDD VDD VDD 10k 100k
13
DIR_CNT
I
High: 2.5V Low: 0.8V OPEN High
13
VDD
10k 100k 20k
Scan direction switch. High: forward scan Low: reverse scan
100k
25
6 17 19 21 27 29 31
GND SH_OUT6
GND
Analog GND.
PVCC
SH_OUT5 SH_OUT4 O SH_OUT3 SH_OUT2 SH_OUT1 2.5 to 11.5V
17 27 19 29 21 31
PVCC 4k 4k 2p
Output.
4k
VCC VCC 70 VCC
33
VCOMOUT
O
5 to 8V
VCC VCC 2k 34 100k VCC
10 80 500 40k
VCOM output. Can be set to VSIGCEN to VSIGCEN -2V by Pin 34 input. VSIGCEN: voltage set by Pin 35.
200k
1p 500
34
VCOMOFST
I
0 to 10V
33
145
VCOM output setting. Deviation from SIGCEN input is 0 for input setting of 0V. VCOM is set at the minus side from VSIGCEN at high voltage.
VCC 10k
35
SIGCEN
I
7V
35 20
Center voltage of signal inversion setting. Output signal is inverted, centered around this voltage, by FRP high/low. Normally, set to 7V.
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CXA2112R
Pin No.
Symbol
I/O
Standard voltage level
Equivalent circuit
VCC 45 VCC
Description
VCC 10 2k 4p
37
ISET
I
1.35V
145 37
Vcc circuit bias current setting. Normally, connect 27k (1%) between this pin and GND.
VCC VCC 75k 0.2p
38
SID_OUT
O
2.5 to 11.5V
38 75k 0.2p
SID signal waveform output. Connect to an external buffer for panel.
23 26 32
PGND PVCC GND2
GND 15.5V GND
VCC 19.5k
Power GND. Power Vcc. Connect directly to Vcc. Analog GND.
91k 7V 78k
VCC
39
SID_IN
I
2.3 to 3.3V
39 19.5k
SID signal input.
VCC 30k 42 10
42
SID_OFST
I
3.3V
SID signal input offset setting.
VDD
VDD 100k
44
FRP
I
High: 2.5V Low: 0.8V
44
VDD
50k 10k 50k
Invert pulse input. High: inverse Low: non-inverse Refer to Timing Chart.
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CXA2112R
Pin No.
Symbol
I/O
Standard voltage level
Equivalent circuit
Description
VCC
1.9k
45
SH_IN
I
2.5 to 11.5V
45 200
Sample-and-hold circuit common input. Should not be less than 2V.
VCC VCC VCC
VCC 560
46
INV_OUT
O
2.5 to 11.5V
46
Invert amplifier output.
620
VCC VCC 300
47
VIDEO_IN
I
2.0 to 3.3V
145 47
Invert amplifier input.
VCC 30k
48
OFFSET
I
3.3V
48 10
Video signal input offset setting. Inputs 100% white level.
VDD VDD 2k 49
49
DLY_CNT
I
3 to 5V
50
Dot clock phase adjustment.
43
VCC
15.5V
15V power supply.
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CXA2112R
Pin No.
Symbol
I/O
Standard voltage level
Equivalent circuit
VDD
Description
50
MCLK
50
VDD 20k 10
I
PECL differential
1k VDD 100 20k 51 1k
Dot clock input.
51
MCLK/
VDD VDD
52
INV_CNT
I
High: 2.5V Low: 0.8V
10 2k
52
Dot clock phase invert control.
VDD
VDD
54
CLK_OUT I VDD - 0.3V to VDD
54 55 1m
Phase adjusted dot clock output.
55
CLK_OUT/
VDD
VDD VDD 2k 145 2k
59
CLK_IN
I
59
VDD - 0.3V to VDD 61 CLK_IN/ I
100 VDD 145 61
On-chip timing generator clock input. Connect directly to Pins 54 and 55.
VDD VDD VDD 50k 145 62 50k 150k
62
PRG
I
High: 2.5V Low: 0.8V
Horizontal sync signal PRG input. Refer to Timing Chart.
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CXA2112R
Pin No. 53 58
Symbol VDD DGND
I/O
Standard voltage level 5V
Equivalent circuit
Description 5V power supply. Digital GND. Die pad. Used as thermal radiator on board. Connect to GND.
8, 9, 24, 25, D.P 40, 41, 56, 57 7, 11, 14, 15, 16, 18, 20, 22, NC 28, 30, 36, 60, 63, 64
GND
No connection. Not connected to anything.
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CXA2112R
Electrical Characteristics (See Electrical Characteristics Measurement Circuit.) VDD = 5V, VCC = 15.5V, VSIGCEN = 7V, Ta = 25C No.
1 2 3
Item
VDD current consumption Vcc current consumption Invert amplifier gain
Symbol
IDD ICC AINV
Measurement points
IVDD IVCC1 IVCC2 VINV VIN
Measurement contents
IDD = IVDD ICC = IVCC1 + IVCC2 AINV = VINV (AC)/VIN Input a square wave from VIN so that VINV output amplitude is 3.5Vp-p. Measure slew rate at 10 to 90% of output waveform rise or fall. (for inverse or non-inverse) Input 2.5V DC, 100mVp-p AC from Pin 47 (VIDEO_IN) and measure VINV. The frequency that is -3dB to 100kHz. (for inverse/ non-inverse) Invert amplifier delay time difference for inverse and noninverse. ASID = VSID (AC)/VSID_IN Input invert pulse to Pin 44 (FRP), load capacity C7 = 47pF, and apply DC input voltage to VSID_IN so that VSID is 2.5V/11.5V. Measure slew rate at 10 to 90% of output waveform rise or fall. VCOM output voltage when Pin 34 (VCOMOFST) is changed from 0 to 10V.
Min.
22 30 --
Typ. Max. Unit
32 41 2.7 42 52 -- mA mA times
4
Invert amplifier slew rate
SRINV
VINV
--
700
--
V/s
5
Invert amplifier output band width
BWINV
VINV
--
90
--
MHz
6 7
Output delay deviation for inverse/non-inverse SID gain
TDIFF ASID
VINV VSID VSID_IN
-- --
2 4
4 --
ns times
8
SID output slew rate
SRSID
VSID
--
30
--
V/s
9 10
VCOM adjustable range Farst stage S/H slew rate
VCOM SRSH1
VCOM --
Vsig - 2 or less --
-- 700
Vsig --
V V/s
First stage S/H slew rate on Block Diagram. Input a square wave from VIN so that VOUT1 to VOUT6 output amplitude is 3.5Vp-p. Measure slew rate at 10 to 90% of output waveform rise or fall. (load 270pF, for inverse or non-inverse) Apply DC voltage to VIN so that VINV (SH_IN) is 6V. Highest frequency for fCLK output at correct timing. Lowest frequency for fCLK output at correct timing. Maximum voltage at which sample-and-hold output (SH_OUT1 to SH_OUT6) can be output. Minimum voltage at which sample-and-hold output (SH_OUT1 to SH_OUT6) can be output.
11
SH_OUT slew rate
SROUT
VOUT1 to VOUT6
--
150
--
V/s
12 13 14
Output deviation between channels Dot clock input highest frequency Dot clock input lowest frequency Maximum output voltage
DOUT fCLKH fCLKL
VOUT1 to VOUT6 fCLK fCLK VOUT1 to VOUT6
-- 100
3 115 12
10
mVp-p MHz
20
MHz
15
VMAX
13
13.5
V
16
Minimum output voltage
VMIN
VOUT1 to VOUT6
2
2.5
V
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CXA2112R
Minimum VOUT1 to VOUT6 value subtracted from maximum VOUT1 to VOUT6 value. Unless otherwise specified, pin setting conditions are as follows. (48) OFFSET = 3.3V, (47) VIDEO_IN = 2.0V, (42) SID_OFST = 3.3V, (39) SID_IN = 2.3V, (35) SIGCEN = 7.0V, (34) VCOMOFST = 0.0V, (1) POS_CNT1 = 0.0V, (2) POS_CNT2 = 0.0V, (5) F/R_CNT = 5.0V, (10) S/12_CNT = 5.0V, (13) DIR_CNT = 5.0V, (49) DLY_CNT = 4.0V, (52) INV_CNT = 5.0V, (44) FRP = 0.0V, fCLK = 65MHz
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CXA2112R
Electrical Characteristics Measurement Circuit
VCC 2.3V VSID_IN 20k VCC VINV VCC VIN 2V 3.3V 3.3V 27k VSID C7 20k
VCOMOFST
SID_OUT
VCOMOUT
VIDEO_IN
INV_OUT
SID_OFST
OFFSET
SH_IN
SID_IN
IVCC1
ISET
FRP
D.P
D.P
48 DLY_CNT DIFF BUFFER2 Frequency fCLK P N VDD SW4 VDD MCLK MCLK/ INV_CNT VDD CLK_OUT CLK_OUT/ D.P D.P DGND CLK_IN NC CLK_IN/ 61 PRG NC NC 64 62 63
47
46
45
44
43
42
41
40
39
38
37
36
SIGCEN
VCOM
VCC
NC
35
34
33 GND2 SH_OUT1 NC C1 270pF SH_OUT2 NC C2 270pF SH_OUT3 PVCC D.P D.P PGND NC SH_OUT4 NC C4 270pF SH_OUT5 NC C5 270pF SH_OUT6 VOUT6 C6 270pF 16 VOUT5 VOUT4 IVCC2 VCC VOUT3 C3 270pF VOUT2 VOUT1
49 50 51 52 S/H 53 54 55 OFFSET CANCEL 56 57 58 59 60 TIMING GENERATOR S/H Pulses S/H S/H S/H S/H BUFFER D CLOCK DELAY S/H S/H S/H BUFFER INVERT AMP SID BIAS VCOM
32 31 30 29 28 OFFSET CANCEL 27 S/H S/H BUFFER 26 25 24 BUFFER 23 22 BUFFER 21 20 BUFFER 19 18 17
OFFSET CANCEL S/H S/H
OFFSET CANCEL S/H S/H S/H
OFFSET CANCEL offset cancel mode timing S/H S/H S/H
OFFSET CANCEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
POS_CNT1
D.P
NC
POS_CNT2
D.P
NC
NEXT_OUT
S/12_CNT
NEXT_IN
F/R_CNT
NC
GND
ENB
VDD VDD SW1 SW2
DIR_CNT
NC
VDD SW3 VCC 15.5V VDD 5V
- 11 -
NC
CXA2112R
Description of Operation 1. INVERT_AMP The VIDEO signal from VIDEO_IN (Pin 47) is amplified about 2.7 times at INVERT_AMP. Its output is INV_OUT (Pin 46). Status of INVERT_AMP is determined by FRP (Pin 44) input (high: inverse, low: noninverse). Invert operation is carried out with SIGCEN (Pin 35) potential as center voltage of signal inversion. OFFSET (Pin 48) input voltage corresponds to 100% white level of the signal input to VIDEO_IN. When used in combination with the CXA2111R, connect the CXA2111R V33 (Pin 8) output to the CXA2112R OFFSET. When use DA converter output as the VIDEO signal, connect DA converter maximum output voltage (normally, DA converter's supply voltage).
OFFSET level
VIDEO IN VIN
FRP
Output level when input is up to OFFSET level approx. 2.7 x VIN
approx. 1V INV_OUT approx. 1V SIGCEN potential
2. SID The signal input to SID_IN (Pin 39) is folded by SIGCEN potential, the same as for INVERT_AMP operation, and outputs to SID_OUT (Pin 38). Gain is about 4 times. SID_OFST (Pin 42) operates in the same way as OFFSET input for INVERT_AMP. In combination with the CXA2111R, connect the CXA2111R SID_OUT (Pin 6) to the CXA2112R SID_IN, and CXA2111R V33 (Pin 8) to the CXA2112R SID_OFST.
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CXA2112R
SID_OFST level SID IN VSID_IN
FRP
Output level when input is up to SID_OFST level approx. 4 x VSID_IN approx. 1V approx. 1V
SIGCEN potential
The SID output is prepared for the Sony LCD panel's (LCX017 and LCX016) uniformity improvement signal input (Psig input). SID_OUT does not have the capability to drive those pins directly. Connect via a buffer. 3. VCOM VCOM generates the DC voltage applied to the Sony LCD panel COM electrode. VCOMOUT (Pin 33) voltage is set as the deviation relative to SIGCEN voltage. When VCOMOFST (Pin 34) is changed from 0 to 10V, VCOMOUT changes from (SIGCEN potential) to (SIGCEN potential) - 2V.
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CXA2112R
4. De-Multiplexer SH_IN (Pin 45) input is de-multiplexed in order from SH_OUT1 (Pin 31) to SH_OUT6 (Pin 17) according to internal timing generator setting, and then is output. Output phase is made simultaneous by the 3-stage sample-and-hold circuit. The waveform example below shows this operation for forward scan, 6-output de-multiplexing.
A C SH_IN B CLK_IN 1 2 3 4
D F E
G H I J
K
L
5
6
7
8
9
10
11
12 A
13
14
15 G
SH_OUT1 0V H SH_OUT2 B 0V C SH_OUT3 I 0V D SH_OUT4 0V K SH_OUT5 E 0V F SH_OUT6 L 0V J
Depending on the operation mode setting, scan direction (SH_OUT1 SH_OUT6 and SH_OUT6 SH_OUT1), number of outputs (6-output/12-output) and sample-and-hold position (output phase) can be changed.
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CXA2112R
5. Operation Mode Setting 1) For each RGB channel, LCX016 requires demultiplexed 6 analog outputs (one CXA2112R), and LCX017 needs 12 (two CXA2112R). In either case, scan direction switching, sample-and-hold position and phase can be controlled. The mode input pin settings for each case are shown below. Fixed Mode Setting LCX016 6-outputs S/12_CNT (Pin 10) F/R_CNT (Pin 5) NEXT_IN (Pin 4) NEXT_OUT (Pin 3) High X1 Short LCX017 "FRONT" half of 12 outputs2 Low High "REAR" half of 12 outputs2 Low Low 2 "FRONT": input data sampling begins from "FRONT" chip for forward scan direction (DIR_CNT high).
Connect to the other NEXT_OUT Connect to the other NEXT_IN 1 X: Don't Care
Table B
2) Scan direction switching DIR_CNT (Pin 13) high gives forward scan, and low gives reverse scan. For forward scan, the input signal level time series is output in descending order from SH_OUT1, and for reverse scan, in descending order from SH_OUT6. For 12-output, SH_OUT6 and SH_OUT1 operated as if connected in order. 3) Sample-and-hold position setting Output's phase can be changed by the voltage applied to POS_CNT1 (Pin 1) and POS_CNT2 (Pin 2). This setting is done for adjustment of the LCD panel input signal timing. Each input pin has 4 setting values, for a total of 16 settings. POS_CNT1 is lower, POS_CNT2 is upper, and each setting values are as shown in Table A-1.
Setting Voltage Range for Sample-and-Hold Position Setting value 0 1 2 3 Threshold GND to 0.75V 1.15 to 1.50V 1.70 to 2.55V 2.95 to VDD Table A-1
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CXA2112R
There are two ways to use these pins. A. Connect directly to the CXA2111R. Connect to the corresponding CXA2111R pins POS_CNT1 and POS_CNT2. This allows bit setting via the CXA2111R register controlled by I2C bus. B. Connect to CMOS logic. Connect CMOS logic as shown in the diagram. See Table A-2. CMOS Logic Connection Setting Value and CMOS Output Pins Setting value 0 1 2 3 a L Hi-Z Hi-Z H Table A-2 b
a CXA2112R Supply voltage C M VMOS O S b R1
L L H H
1 POS_CNT1 (2) (POS_CNT2)
R1 sets the level for setting values 1 and 2. The appropriate resistance value changes depending on numbers of CXA2112R are driven by one CMOS logic (1-channel or RGB 3-channel drive, or one CXA2112R (6outputs/ch) or two CXA2112R (12-outputs/ch)). Recommended resistance values are given in Table A-3. CMOS Logic Connection Usage of CXA2112R and Threshold Setting Resistor R1 RGB 1-channel drive RGB 3-channel drive
6-outputs 12-outputs 6-outputs 12-outputs R1 value 270k 150k Table A-3 100k 47k
VMOS = 3.3 to 5V
- 16 -
CXA2112R
6. Dot Clock Phase Adjustment The CXA2112R has phase adjustment function for input dot clock to achieve high precision and stable operation. High definition images with no jitter and flicker can be reproduced by this adjustment. De-multiplexer operation timing is generated from the clock input to CLK_IN (Pin 59) and CLK_IN/ (Pin 61) (ECL differential). By connecting CLK_OUT (Pin 54) and CLK_OUT/ (Pin 55) to CLK IN/, phase adjusted clock can be used for its timing generation. The CLOCK DELAY block is a PLL clock generator that uses MCLK (Pin 50) and MCLK/ (Pin 51) ECL differential input clock as reference. The CLK_OUT polarity, inverted/non-inverted can be switched by high/low of INV_CNT (Pin 52) input. Also, in the DLY_CNT (Pin 49) input voltage range of 3 to 5V, CLK_OUT phase relative to MCLK can be changed continuously 180deg. (PHDLY in the diagram below.) It also has the advantage that an MCLK with noise can be shaped and used on the board.
MCLK
PHDLY
CLK_OUT
SH_IN
7. Usage of CXA2112R in 12-outputs Two CXA2112Rs are required for 12-outputs, as shown in Application Circuit 2. Please note that the following precautions. * Input the same clock to both ICs' timing generator clock input pins CLK_IN and CLK_IN/. To be concrete, connect one CLK_OUT and CLK_OUT/ to both ICs' CLK_IN and CLK_IN/. At this time, the other CLK_OUT and CLK_OUT/ are not used, but be sure to input the same clock to MCLK and MCLK/ inputs. * Connect both ICs' SH_INs to only one ICs' INV_OUT. At that time, connect the other ICs' VIDEO_IN and OFFSET to 5V. In the same way, connect the other ICs' SID_IN and SID_OFST to 5V. * When only one IC is used for all of INVET_AMP, SID and VCOM, the FRP input on the other IC does not have to be at the timing in the above paragraph, but can be connected to GND. * Short ENB, PRG, POS_CNT1, POS_CNT2, DIR_CNT, INV_CNT and DLY_CNT at both ICs, and apply the same signals.
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CXA2112R
Notes on Operation 1. Signal input timings to the timing generator Input Signal Timing Chart
30CLK or more ENB
PRG
60CLK or more
4CLK or more
FRP 0 to 5CLK
Maintain the relationship in the timing chart. While PRG is high, video input signal must not be changed. The same name output from Sony's LCD timing generators CXD2442Q and CXD2453Q satisfy the above conditions. If the above timing does not be satisfied, timing violation may cause decay of characteristics or IC damage in some case. Especially do not input FRP pulse without ENB and PRG input. We strongly recommend to verify the design on this timings and presence of ENB and PRG.
2. Notes on Mounting * Please be sure that the wiring for internal timing generator link pins NEXT_IN (Pin 4) and NEXT_OUT (Pin 3) is as short as possible, in especially 12-outputs. Also, do not locate a large amplitude high-speed signal path (such as CMOS logic) near the wiring. * The eight pins 8, 9, 24, 25, 40, 41, 56 and 57 are connected to the "die pad" inside the package. A good thermal radiation effect can be achieved by a thick connection to GND plane. * Be sure to short PVcc (Pin 26) and Vcc (Pin 43) so that they go on and off simultaneously.
3. Input Video Signal * Please be sure that the video signal amplitude (0% black level to 100% white level) which inputs to sample and hold (SH_IN (Pin 45)) does not exceed 3.5VPP. Also, as for inputting to sample and hold, do not apply DC level of 2V or lower during operation.
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CXA2112R
Application Circuit 1
BUFFER VCC 47
0.1
3.3k 3.3
VCC 5.1k 10k 0.1 5.1k
100 3.3k VCC
3.3
1
20k 0.1
0.1
VCOMOFST 34
SID_OUT
OFFSET
SH_IN
SID_IN
VCC
ISET
FRP
D.P
D.P
CLK H 32 CXA3106Q CLK L 31 DLY_CNT MCLK SID_OUT 6 V33 8 R_OUT 18 G_OUT 16 CLK_OUT/ B_OUT 14 CXA2111R DLY_CNT 3 INV_CNT 5 POS_CNT1 1 POS_CNT2 2 DIR_CNT 4 VDD 10 0.1 CLK_IN NC CLK_IN/ 61 PRG NC NC FRP 30 CXD2442Q PRG 29 ENB 60 64 62 63 D.P DGND D.P MCLK/ INV_CNT VDD CLK_OUT 49 50 51 52
48
47
46
45
44
43
42
41
40
39
38
37
36
SIGCEN
27k NC
35
VCOMOUT 33 GND2 SH_OUT1 NC SH_OUT2 NC SH_OUT3 PVCC D.P 7 SIG1 D.P PGND NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 4 SIG5 6 SIG6 0.1 10 5 SIG2 3 SIG3 2 SIG4 LCX016 LCD panel VCC 1 PSIG 24 COM
VIDEO_IN
INV_OUT
SID_OFST
32 INVERT AMP SID BIAS VCOM 31 30 29 S/H S/H S/H BUFFER 28 CLOCK DELAY OFFSET CANCEL 27 S/H S/H S/H BUFFER 26 OFFSET CANCEL S/H S/H Pulses TIMING GENERATOR S/H S/H BUFFER 25 24 BUFFER 23 22 BUFFER 21 20 BUFFER 19 18 17 D
53 54 55 56 57 58 59 60
OFFSET CANCEL S/H S/H S/H
OFFSET CANCEL S/H S/H S/H
OFFSET CANCEL offset cancel mode timing S/H S/H S/H
OFFSET CANCEL
1 POS_CNT1
2 POS_CNT2
3 NEXT_OUT NEXT_IN
4 F/R_CNT
5
6 GND
7 NC
8 D.P D.P
9
10 S/12_CNT
11 NC
12 ENB
13 DIR_CNT
14 NC
15 NC
16 NC
VCC 15.5V
VDD 5V
Open or High (5V)
Open or High (5V)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXA2112R
VCC
Application Circuit 2
20k
VCC 20k BUFFER SID_OUT 6 1 PSIG
VCOMOFST
B_OUT 14 VIDEO_IN INV_OUT OFFSET SH_IN
VCC SID_OFST SID_OUT SIGCEN 27k ISET NC SID_IN
FRP
VCC
G_OUT 16
D.P
R_OUT 18 DLY_CNT MCLK V33 8 MCLK/ INV_CNT VDD DIR_CNT 4 VDD CLK_OUT CLK_OUT/ D.P POS_CNT1 1 D.P DGND CLK_IN NC CLK_IN/ 61 PRG NC NC FRP 45 CXD2453Q PRG 48 64 62 63
D.P
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VCOMOUT
31 COM
33 GND2 SH_OUT1 NC SH_OUT2 NC SH_OUT3 PVCC D.P D.P PGND NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 8 VSIG6 7 VSIG5 6 VSIG4 VCC 5 VSIG3 4 VSIG2 3 VSIG1
DLY_CNT 3 CXA2111R
49 50 51 52 S/H 53 54 55 OFFSET CANCEL 56 57 58 59 60 TIMING GENERATOR S/H Pulses S/H S/H S/H S/H BUFFER D CLOCK DELAY S/H S/H S/H BUFFER INVERT AMP SID BIAS VCOM
32 31 30 29 28 OFFSET CANCEL 27 S/H S/H BUFFER 26 25 24 BUFFER 23 22 BUFFER 21 20 BUFFER 19 18 17
INV_CNT 5
POS_CNT2 2
OFFSET CANCEL S/H S/H
OFFSET CANCEL S/H S/H S/H
OFFSET CANCEL offset cancel mode timing S/H S/H S/H
OFFSET CANCEL
1 POS_CNT1 POS_CNT2
2
3 NEXT_OUT
4 NEXT_IN
5 F/R_CNT
6 GND NC
7
8 D.P
9 D.P
10 S/12_CNT
11 NC
12 ENB
13 DIR_CNT
14 NC
15 NC
16 NC
ENB 47
VDD LCX017
S/12_CNT
CXA3106Q CLK L 31
D.P
D.P
NC
DIR_CNT
NEXT_IN
F/R_CNT
CLK H 32
NEXT_OUT
POS_CNT1
POS_CNT2
GND
ENB
NC
NC
NC 15
1 NC NC PRG CLK_IN/ NC CLK_IN DGND D.P D.P CLK_OUT/ CLK_OUT VDD VDD INV_CNT MCLK/ MCLK DLY_CNT
2
3
4
5
6
7
8
9
10
11
12
13
14
NC 16 SH_OUT6 NC SH_OUT5 NC SH_OUT4 NC PGND D.P D.P PVCC SH_OUT3 NC SH_OUT2 NC SH_OUT1 GND2 9 VSIG7 10 VSIG8 VCC 11 VSIG9 12 VSIG10 13 VSIG11
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 INVERT AMP SID BIAS VCOM D S/H CLOCK DELAY S/H S/H S/H BUFFER S/H TIMING GENERATOR S/H Pulses S/H offset cancel mode timing S/H OFFSET CANCEL S/H S/H BUFFER
17 18 19 20 BUFFER 21 22 BUFFER 23 24 BUFFER 25 26 27 OFFSET CANCEL 28 S/H S/H BUFFER 29 30 31 32
14 VSIG12
OFFSET CANCEL S/H S/H
OFFSET CANCEL S/H S/H S/H
OFFSET CANCEL S/H S/H
OFFSET CANCEL
48 OFFSET
47 VIDEO_IN
46 INV_OUT
45 SH_IN
44 FRP
43 VCC
42 SID_OFST
41 D.P
40 D.P
39 SID_IN
38 SID_OUT
37 ISET
36 NC
35 SIGCEN
34 VCOMOFST VDD
33 VCOMOUT
VCC VDD VDD VDD
27k
VCC 15.5V
VDD 5V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 20 -
CXA2112R
Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, SIGCEN = 7.0V, Ta = 25C)
CLK_OUT phase to MCLK vs. DLY_CNT voltage (1) CLK_OUT phase to MCLK vs. DLY_CNT voltage (2)
180 fCLK = 20MHz 120 INV_CNT = High 180 120 fCLK = 100MHz
Phase [deg]
60 INV_CNT = Low 0 -60 -120 -180 2.5 INV_CNT = High
Phase [deg]
60 0 -60 -120 INV_CNT = Low -180 INV_CNT = Low INV_CNT = High
3 3.5 4 4.5 DLY_CNT (Pin 49) voltage [V]
5
2.5
3 3.5 4 4.5 DLY_CNT (Pin 49) voltage [V]
5
SID_OUT voltage vs. SID_OFST voltage (1)
16
SID_OUT voltage vs. SID_OFST voltage (2)
12
SID_OUT (Pin 38) voltage [V]
14 12
SID_OUT (Pin 38) voltage [V]
SID_IN = 2.300V
SID_IN = 4.000V 10 8 6 4 FRP = Low 2 0 FRP = High
FRP = High 10 8 6 4 2 0 0 1 2 3 4 SID_OFST (Pin 42) voltage [V] 5 FRP = Low
0
1 2 3 4 SID_OFST (Pin 42) voltage [V]
5
SID_OUT voltage vs. SID_IN voltage (1)
16 16
SID_OUT voltage vs. SID_IN voltage (2)
SID_OUT (Pin 38) voltage [V]
14 12 10 8 6 4 2 0 0 1 2 3 4 SID_IN (Pin 39) voltage [V] 5 FRP = Low SID_OFST = 5.000V FRP = High
SID_OUT (Pin 38) voltage [V]
14 12
SID_OFST = 3.300V
FRP = High 10 8 6 4 2 0 0 1 2 3 4 SID_IN (Pin 39) voltage [V] 5 FRP = Low
- 21 -
CXA2112R
INV_OUT voltage vs. OFFSET voltage (1)
14
INV_OUT voltage vs. OFFSET voltage (2)
14
INV_OUT (Pin 46) voltage [V]
12 10 8 6 4 2 0 0 1 2 3 4 OFFSET (Pin48) voltage [V] 5 FRP = Low FRP = High
INV_OUT (Pin 46) voltage [V]
VIDEO_IN = 1.800V
VIDEO_IN = 3.500V 12 10 8 6 4 2 0 0 1 2 3 4 OFFSET (Pin48) voltage [V] 5 FRP = Low FRP = High
INV_OUT voltage vs. VIDEO_IN voltage (1)
14
INV_OUT voltage vs. VIDEO_IN voltage (2)
14
INV_OUT (Pin 46) voltage [V]
12 10 8 6 4 2 0 0 1 2 3 4 VIDEO_IN (Pin 47) voltage [V] 5 FRP = Low FRP = High
INV_OUT (Pin 46) voltage [V]
OFFSET = 3.300V
OFFSET =5.000V 12 10 8 6 4 2 0 0 1 2 3 4 VIDEO_IN (Pin 47) voltage [V] 5 FRP = Low FRP = High
VCOMOUT voltage vs. VCOMOFST voltage
8
VCOMOUT (Pin 33) voltage [V]
7 6 5 4 3 2 1 0 0 2 4 6 12 14 8 10 VCOMOFST (Pin 34) voltage [V]
- 22 -
CXA2112R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
16.0 0.2 48 49 14.0 0.1 33 32 0.1 1.7MAX
B A 17 1 0.8 16 0.13 M
64
0.25 0.1 0.1 + 0.08 0.37 - 0.07
(0.5)
DETAIL B
EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.7g
+ 0.08 0.37 - 0.07
(15.0) (0.5)
0 to 10 DETAIL A NOTE: Dimension "" does not include mold protrusion.
0.6 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L02 LQFP064-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 23 -
(0.125)
(0.35)
0.145 0.04

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